Majority Logic Synthesis for Area Delay Trade-off in Emerging Technologies

Abstract

This letter presents a novel majority logic synthesis (MLS) which optimize area delay trade-off using a novel cost of circuit (CoC) parameter. The CoC overcome the problem faced by previous synthesis algorithms, which were mainly focused on the area or delay optimization. Experiments on microelectronics center of North Carolina (MCNC) benchmarks indicate that the proposed approach has achieved an average reduction of 36% in delay, and an average reduction of 15% in cost of circuit with a 1.5% overhead in the area.