Cost Aware Majority Logic Synthesis for Emerging Technologies

Abstract

Continuous growth of semiconductor industry-based n More’s law is in danger due to the physical limitation of CMOS technology. In order to sustain more’s law, researchers are aggressively discovering other alternatives such as nano magnetic logic (NML) and quantum dot cellular automata (QCA). Majority gate is the base element for these technologies for synthesis of logic circuit. This paper presents a novel majority logic synthesis (MLS) which optimize Area delay using a novel Cost of Circuit (CoC) parameter during the synthesis process which was faced by currently available synthesis algorithms which are mainly focused on area optimization. In addition, an updated library is presented for majority logic synthesis based on 3-input(M3) and 5-input(m5) majority gates for area-Delay optimization during MLS. Experiments on microelectronics center of North Carolina (MCNC) benchmarks indicate that, the proposed approach has achieved an average reduction of 39% in delay, an average reduction of 14% in cost of circuit with the 2% overhead in the circuit are