A Heuristic-Driven and Cost Effective Majority/ Minority Logic Synthesis for Post-CMOS Emerging Technology

Abstract

Due to the physical restriction of current CMOS technology, emerging technologies that have majority logic gate as a base component are being explored. The process of transforming from boolean network to the majority logic network is called majority logic synthesis. Hence, the contributions of this work is as follows: (i) a novel heuristic-driven tabular approach for majority logic synthesis has been presented that overcomes the scalability problem of previous synthesis algorithms, (ii) a heuristic named as matching difference (MD) is proposed to guide the synthesis process, (iii) a parameter named as cost of circuit (CoC) is proposed to maintain the trade-off between area and delay during majority logic synthesis, (iv) an extended library for majority logic synthesis based on 3-input and 5-input majority gates that help in delay reduction of majority circuit is presented, and (v) a post-synthesis optimization method is proposed based on majority algebra. Based on experiments with MCNC benchmarks, it is verified that the proposed approach accomplishes an average diminution of 24% at the majority level and 31% in the majority gate count. Further, while executing a case study with quantum dot cellular automata(QCA), the proposed methodology is able to achieve an average diminution of 36% in delay and 15% in circuit cost with a penalty of 2% in the area.